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MEMORY COHERENCE IN A MULTI-CORE, MULTI-LEVEL, HETEROGENEOUS COMPUTER ARCHITECTURE
MEMORY COHERENCE IN A MULTI-CORE, MULTI-LEVEL, HETEROGENEOUS COMPUTER ARCHITECTURE
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机译:多核,多层次,异构计算机体系结构中的内存一致性
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摘要
Techniques are described for memory coherence in a multi-core system with a heterogeneous memory architecture comprising one or more hardware-managed caches and one or more software-managed caches. According to one embodiment, a set of one or more buffers are allocated in memory, and each respective buffer is associated with a respective metadata tag. The metadata tag may be used to store metadata that identifies a state associated with the respective buffer. The multi-core system may enforce coherence for the one or more hardware-managed caches and the one or more software-managed caches based on the metadata stored in the metadata tag for each respective buffer in the set of one or more buffers. The multi-core system may read the metadata to determine whether a particular buffer is in a hardware-managed or a software-managed cacheable state. Based on the current state of the particular buffer, the multi-core system may perform coherence operations.
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