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LINEAR COMPLEXITY PRIORITIZATION OF TIMING ENGINEERING CHANGE ORDER FAILURES

机译:时序工程变更订单故障的线性复杂性优先级

摘要

A system and a method are disclosed for displaying an output of a static timing analysis. A plurality of timing violations of an integrated circuit is identified. The timing violations are associated with a timing path. A reason is identified for each of the timing violations. A priority for fixing the timing violations is determined. Information describing the timing violations is sent for being presented. The information presented includes an information indicating priority associated with timing violations to assist developers in prioritizing tasks for fixing the timing violations.
机译:公开了一种用于显示静态时序分析的输出的系统和方法。识别出集成电路的多个时序违规。时序违规与时序路径相关联。确定每个时序违规的原因。确定修复定时违规的优先级。发送描述时序违规的信息以供呈现。呈现的信息包括指示与时序违规相关联的优先级的信息,以帮助开发人员确定修复时序违规的任务的优先级。

著录项

  • 公开/公告号US2016085901A1

    专利类型

  • 公开/公告日2016-03-24

    原文格式PDF

  • 申请/专利权人 SYNOPSYS INC.;

    申请/专利号US201414491808

  • 发明设计人 NAHMSUK OH;SEUNGWHUN PAIK;JIA WANG;

    申请日2014-09-19

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 14:35:12

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