首页> 外国专利> Integrated circuit and method for accessing segments of a cache line in arrays of storage elements of a folded cache

Integrated circuit and method for accessing segments of a cache line in arrays of storage elements of a folded cache

机译:用于访问折叠式高速缓存的存储元件阵列中的高速缓存行的段的集成电路和方法

摘要

An integrated circuit including a cache and first and second modules. The cache is folded a predetermined number of times. The cache includes arrays and storage elements. Each of the arrays includes respective ones of the storage elements. The arrays store a cache line. The cache line includes segments of data. The segments of data are stored in two or more of the arrays. Each of the segments of data is stored in a corresponding one of the storage elements. The first module receives a first identifier of one of the segments of data and a second identifier of a set of the storage elements. The first module determines an index based on the first and second identifiers. The second module, based on the index, accesses one of the segments of data from the two or more of the arrays and outputs the one of the segments of data.
机译:一种包括高速缓存以及第一模块和第二模块的集成电路。高速缓存被折叠预定次数。高速缓存包括阵列和存储元素。每个阵列包括各自的存储元件。阵列存储高速缓存行。高速缓存行包括数据段。数据段存储在两个或多个数组中。每个数据段都存储在相应的一个存储元素中。第一模块接收数据段之一的第一标识符和一组存储元件的第二标识符。第一模块基于第一和第二标识符来确定索引。第二模块基于索引,从两个或多个阵列访问数据段之一,并输出数据段之一。

著录项

  • 公开/公告号US9367456B1

    专利类型

  • 公开/公告日2016-06-14

    原文格式PDF

  • 申请/专利权人 MARVELL INTERNATIONAL LTD.;

    申请/专利号US201414288739

  • 发明设计人 KIM SCHUTTENBERG;RICHARD BRYANT;

    申请日2014-05-28

  • 分类号G06F12;G06F12/08;

  • 国家 US

  • 入库时间 2022-08-21 14:31:40

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号