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Integrated circuit and method for accessing segments of a cache line in arrays of storage elements of a folded cache
Integrated circuit and method for accessing segments of a cache line in arrays of storage elements of a folded cache
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机译:用于访问折叠式高速缓存的存储元件阵列中的高速缓存行的段的集成电路和方法
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摘要
An integrated circuit including a cache and first and second modules. The cache is folded a predetermined number of times. The cache includes arrays and storage elements. Each of the arrays includes respective ones of the storage elements. The arrays store a cache line. The cache line includes segments of data. The segments of data are stored in two or more of the arrays. Each of the segments of data is stored in a corresponding one of the storage elements. The first module receives a first identifier of one of the segments of data and a second identifier of a set of the storage elements. The first module determines an index based on the first and second identifiers. The second module, based on the index, accesses one of the segments of data from the two or more of the arrays and outputs the one of the segments of data.
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