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Low-latency, frequency-agile clock multiplier

机译:低延迟,频率捷变时钟乘法器

摘要

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
机译:在第一时钟频率倍增器中,具有频谱交错的锁定范围的多个注入锁定振荡器(ILO)并行操作,以实现一个集体输入频率范围,该范围实质上比单独的ILO的范围宽。在每个输入频率改变之后,可以根据一个或多个合格标准来评估ILO输出时钟,以选择一个ILO作为最终时钟源。在第二个时钟倍频器中,灵活注入速率注入锁定振荡器锁定至超谐波,次谐波或频率注入脉冲,在不同注入脉冲速率之间无缝过渡,以实现较宽的输入频率范围。由第一和/或第二时钟倍频器响应于输入时钟而影响的倍频因子是在运行中确定的,然后与已编程的(期望的)倍频因子进行比较,以在倍频的不同分频实例之间进行选择时钟。

著录项

  • 公开/公告号US9344074B2

    专利类型

  • 公开/公告日2016-05-17

    原文格式PDF

  • 申请/专利权人 RAMBUS INC.;

    申请/专利号US201414565802

  • 申请日2014-12-10

  • 分类号H03K5/13;H03L7/06;H03L7/099;H03K5;H03L7/16;

  • 国家 US

  • 入库时间 2022-08-21 14:31:31

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