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Method for reducing gate height variation due to overlapping masks

机译:减少由于重叠掩模引起的栅极高度变化的方法

摘要

A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.
机译:一种方法包括在半导体衬底中形成至少一个鳍。在鳍片上方形成占位栅结构。占位符栅极结构包括占位符材料和在占位符材料的顶表面上限定的盖结构。盖结构包括设置在占位符材料上方的第一盖层和设置在第一盖层上方的第二盖层。在第二覆盖层的至少一部分上执行氧化工艺,以在第二覆盖层的其余部分上方形成氧化区域。去除一部分氧化区域以暴露剩余部分。第二覆盖层的剩余部分被去除。去除第一覆盖层以暴露出占位材料。占位符材料替换为导电材料。

著录项

  • 公开/公告号US9401416B2

    专利类型

  • 公开/公告日2016-07-26

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201414560035

  • 申请日2014-12-04

  • 分类号H01L21/768;H01L29/66;H01L21/02;H01L21/3105;

  • 国家 US

  • 入库时间 2022-08-21 14:30:36

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