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Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

机译:半导体器件和形成具有导电焊盘的互连结构的方法,该导电焊盘具有扩大的互连表面积以增强互连性能

摘要

A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.
机译:半导体器件具有衬底和形成在衬底上方的第一导电焊盘。通过在第一导电焊盘中形成多个凹部来扩大第一导电焊盘的互连表面积。凹部可以是同心环的布置,圆形凹部的布置或平行的线性沟槽的布置。可替代地,通过在第一导电焊盘上方形成第二导电焊盘来扩展第一导电焊盘的互连表面积。半导体管芯具有形成在半导体管芯的表面上方的多个互连结构。半导体管芯以互连结构接触第一导电焊盘的扩展互连表面积的方式安装到基板,以增加互连结构与第一导电焊盘的结合强度。模具底部填充材料沉积在半导体管芯和基板之间。

著录项

  • 公开/公告号US9373578B2

    专利类型

  • 公开/公告日2016-06-21

    原文格式PDF

  • 申请/专利权人 STATS CHIPPAC LTD.;

    申请/专利号US201414192706

  • 发明设计人 OHHAN KIM;SUNGWON CHO;DAESIK CHOI;

    申请日2014-02-27

  • 分类号H01L21/44;H01L23/52;H01L23/522;H01L21/56;H01L23/498;H01L23/00;

  • 国家 US

  • 入库时间 2022-08-21 14:30:29

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