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Lane error detection and lane removal mechanism to reduce the probability of data corruption

机译:通道错误检测和通道删除机制可减少数据损坏的可能性

摘要

Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.
机译:用于检测车道错误并去除多车道链路中的错误车道的方法,装置和系统。包括链接分组的数据被分成多个比特流,并在多车道链接的各个通道上并行发送。在接收器端口的多个接收通道上接收比特流数据,并对其进行处理以重组链接数据包,并计算在每个通道上接收的数据的CRC。链路分组包括发送的CRC,将其与接收的CRC进行比较以检测链路分组错误。在检测到链路数据包错误时,将存储每个通道或每个传输组的CRC值,并发出重试请求以重传错误的数据包。结合接收到重发的数据包,将对接收到的数据重新计算每个通道或每个传输组的CRC值,并将其与存储的每个通道或每个传输组的CRC值进行比较,以检测导致链路数据包错误的通道。

著录项

  • 公开/公告号US9325449B2

    专利类型

  • 公开/公告日2016-04-26

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201314099345

  • 发明设计人 MARK S. BIRRITTELLA;

    申请日2013-12-06

  • 分类号H03M13;G06F11/10;H04L1;H03M13/09;

  • 国家 US

  • 入库时间 2022-08-21 14:30:15

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