Methods and apparatus for detecting and correcting errors in high-speed serial communications systems

摘要

An error detection and correction circuit is provided that reduces the number of errors in a data signal sent over a high-speed serial link with little area overhead and without deteriorating the latency of the data transmission. An error detection and correction circuit on the transmit side may compute parity bits for each data packet of N bit-wise interleaved data packets and insert these parity bits into a serial data stream. A transmitter may send the serial data stream with the data packets and the parity bits over a high-speed serial link to a receiver. An error detection and correction circuit on the receive side may locate and correct single-bit errors and detect double-bit errors in each packet of the data signal. Thus, the error correction circuit may correct up to N errors in the N bit-wise interleaved data packets.