Emulated message signaled interrupts in a virtualization environment

摘要

A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a host physical memory address translated from a guest physical memory address in the address space of a virtual machine to which an I/O device has been assigned. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the host physical memory address, emulate a first message signaled interrupt identifying the host physical memory address.