Majority determination circuit, majority determination method, and semiconductor device

摘要

A majority determination circuit includes a first determination unit suitable for determining a first majority between bits of a first logic value and a second logic value in a first odd-bit data, wherein the first odd-bit data is an even-bit data with absence of first bit, a second determination unit suitable for determining a second majority between bits of the first logic value and the second logic value in a second odd-bit data, wherein the second odd-bit data is the even-bit data with absence of second bit, and a result combination unit suitable for determining a third majority between bits of the first logic value and the second logic value in an even-bit data based on the first majority and the second majority.