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Techniques and configurations associated with a capductor assembly

机译:与电容器组件相关的技术和配置

摘要

Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.
机译:本公开的实施例针对与电容器组件相关联的技术和配置。在一个实施例中,电容器组件可包括半导体晶片和设置在半导体晶片的第一面上的多个电感器。多个电感器可以被嵌入在其上布置有多个互连结构的电绝缘材料中。多个互连结构可以被配置为将多个电感器电耦合至管芯。该IC组件可以进一步包括多个电容器,该多个电容器设置在该晶片的与晶片的第一侧面相对的第二侧面上。所述多个电容器可以与第二多个互连结构电耦合,所述第二多个互连结构可以被配置为将所述多个电容器与管芯电耦合。可以描述和/或要求保护其他实施例。

著录项

  • 公开/公告号US9230944B1

    专利类型

  • 公开/公告日2016-01-05

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201414464484

  • 申请日2014-08-20

  • 分类号H01L21;H01L25/16;H01L49/02;H01L21/56;H01L23/31;H01L21/768;H01L23/528;H01G4/30;H01G4/38;

  • 国家 US

  • 入库时间 2022-08-21 14:27:43

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