SCHEDULING APPARATUS OF MATRIX H FOR VSS ALGORITHM OF LDPC DECODER AND METHOD THEREOF

摘要

The present invention discloses an apparatus and a method for scheduling a matrix H used in a VSS algorithm of a low density parity check (LDPC) decoder. The scheduling method includes the steps of: identifying a row including a memory address in each column of a parity check matrix H; searching for a row which does not include a memory address identical to the memory address among the rows of the parity check matrix H; and scheduling the parity check matrix H such that the row which includes the memory address can be adjacent to the row which does not include the memory address.;COPYRIGHT KIPO 2016