FAULT LOCALIZATION AND ERROR CORRECTION METHOD FOR SELF-CHECKING BINARY SIGNED-DIGIT ADDER, AND DIGITAL LOGIC CIRCUIT TO PERFORM SAME METHOD

摘要

The present invention relates to a fault localization and an error correction method for a self-checking binary signed-digit adder, and a digital logic circuit to perform the same method. More specifically, the present invention relates to a fault localization and an error correction method for a self-checking binary signed-digit adder which can detect a stuck-at-fault of a self-checking binary signed-digit adder with low costs and low complexity and can perform self-correction of an error using a self-dual concept, and a digital logic circuit to perform the same method to perform the same method.;COPYRIGHT KIPO 2016