The invention relates to a non-volatile memory (MA2) on a semiconductor substrate, comprising: a first memory cell comprising a floating gate transistor (TRi, j) and a selection transistor (ST) having a buried vertical control gate ( CSG), a second memory cell (Ci, j + i) comprising a floating gate transistor (TRi, j + i) and a selection transistor (ST) having the same control gate (CSG) as the gate selection transistor. the first memory cell, a first bit line (RBLj) connected to the floating gate transistor (TRi, j) of the first memory cell, and a second bit line (RBLj + 1) connected to the floating gate transistor (TRi, j + i) of the second memory cell (Ci, j + i).
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