REFERENCE CLOCK SAMPLING DIGITAL PLL / FLL

摘要

A digital phase locked loop (DPLL) operates in the frequency domain. The period (and hence frequency) of a reference frequency clock signal is determined by sampling with a (higher frequency) digitally controlled oscillator (DCO) clock. The period is compared to the period representation of a desired frequency, and the frequency error signal is integrated in a loop filter and applied as a control input to the DCO. To prevent spurious emissions resulting from the accumulation of quantization errors in the frequency determination and comparison operations, the arrival time of state transition edges of the reference frequency clock signal are randomized prior to sampling. The edge randomization control signal preferably has a triangular probability density function, and its spectrum has most significant energy outside the loop bandwidth of the DPLL; hence, the spurious emissions caused by the accumulation of quantization errors are filtered out by the loop filter.