A time delay circuit comprising:a first semiconductor substrate (42) including a top planar surface and a bottom surface;a first delay line (46) formed on the top planar surface of the first substrate andhaving a first end and a second end;a metal layer formed on the bottom surface of the first substrate and including an opening;a second semiconductor substrate (44) including a top planar surface and being spaced apart from the first substrate so as to provide an air gap therebetween;a second delay line (58) formed on the top planar surface of the second substrate and having a first end and a second end; andan inter-cavity interconnection electrically coupled to the second ends of the first andsecond delay lines and extending through the first substrate, the opening in the metal layer and the air gap between the first and second substrates.
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