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PROCESSOR INCLUDING MULTIPLE DISSIMILAR PROCESSOR CORES THAT IMPLEMENT DIFFERENT PORTIONS OF INSTRUCTION SET ARCHITECTURE

机译:包含多个异类处理器的处理器,这些异类处理器可实现指令集体系结构的不同部分

摘要

In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.
机译:在一实施例中,集成电路可包括一个或多个处理器。每个处理器可以包括多个处理器核心,并且每个核心具有不同的设计/实现和性能级别。例如,一个内核可以实现为高性能,而另一个内核可以在较低的最大性能下实现,但是可以针对效率进行优化。另外,在一些实施例中,由处理器实现的指令集体系结构的一些特征可以仅在构成处理器的核心之一中实现。如果在不同的内核处于活动状态时通过代码序列调用此功能,则处理器可以将内核交换到实现该功能的内核。可替代地,可以采取异常并且可以执行异常处理程序以识别特征并激活相应的核心。

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