Low-latency serial data encoding scheme for improved burst error resilience

摘要

High performance computer systems and methods use modified header bit encoding to communicate data packets between computing nodes over a multilane communication link. Each data packet is provided with flow control information and error detection information and then divided into payloads per lane. The sync header bits of each payload are added to the payload at non-adjacent locations, thereby reducing the probability that a single correlated burst error will invert both header bits. The encoded blocks including payload and sparse header bits are then transmitted simultaneously on multiple lanes for reception, error detection, and reconstruction by the receiving computing node.