首页> 外国专利> LATCHING DATA FOR OUTPUT AT AN EDGE OF A CLOCK SIGNAL GENERATED IN RESPONSE TO AN EDGE OF ANOTHER CLOCK SIGNAL

LATCHING DATA FOR OUTPUT AT AN EDGE OF A CLOCK SIGNAL GENERATED IN RESPONSE TO AN EDGE OF ANOTHER CLOCK SIGNAL

机译:响应于另一个时钟信号的边缘而生成的时钟信号的边缘处的输出的锁存数据

摘要

In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.
机译:在一个示例中,一种操作存储设备以锁存数据以从该存储设备输出的方法可以包括:响应于第二时钟信号的第一时钟边沿而生成第一时钟信号的第一时钟边沿;响应于紧接在第二时钟信号的第一时钟沿之后的第二时钟信号的第二相反的时钟沿,紧接在第一时钟信号的第一时钟沿之后的第一时钟信号的时钟沿,并锁存数据响应于第一时钟信号的第二时钟沿以从存储设备输出。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号