Using Very Long Instruction Word VLIW Cores In Many-Core Architectures

摘要

Current ultra-high-performance computers execute instructions at the rate of roughly 10 PFLOPS and dissipate power in the range of 10 MW. The next generation of exascale machines will need to execute instructions at EFLOPS rates-100× as fast as today's—but without dissipating any more power. To achieve this challenging goal, the emphasis will be on power-efficient execution, and for this we propose VLIW-CMP as a general architectural approach that will improve significantly on the power efficiency of existing solutions. To make VLIW work efficiently, we describe multiple mechanisms: software register-renaming, a hardware facility in which data forwarding is controlled completely by the compiler; and a disjunct register file, which reduces both the die area required by the register file and the power dissipated by the register file. The preferred embodiments disclose power saving methods and devices for use in computers with parallel processing units, or any high-performance processors with multiple pipelines or parallel processing. These power saving methods and devices include especially especially (1) data forwarding and register-file ports, (2) the use of VLIW core architectures to reduce a manycore chip's off-chip memory-bandwidth needs, (3) renaming registers in software, and (4) disjunct register files, which are widely applicable to any processor with multiple pipelines.