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THREAD AND DATA ASSIGNMENT IN MULTI-CORE PROCESSORS

机译:多核处理器中的线程和数据分配

摘要

Technologies are generally described for methods and systems to assign threads in a multi-core processor. In an example, a method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.
机译:通常描述用于在多核处理器中分配线程的方法和系统的技术。在一个示例中,一种在多核处理器中分配线程的方法可以包括响应于第一核和第二核经历的高速缓存未中而确定与获取数据的存储器控​​制器有关的数据。可以基于由各个存储器控制器处理的高速缓存未中的数量将线程分配给核心。方法可以进一步包括确定线程是等待时间绑定或带宽绑定的。可以基于将线程确定为等待时间绑定或带宽绑定来将线程分配给核心。响应于将线程分配给核心,可以将用于线程的数据存储在所分配的核心中。

著录项

  • 公开/公告号US2017228259A1

    专利类型

  • 公开/公告日2017-08-10

    原文格式PDF

  • 申请/专利权人 EMPIRE TECHNOLOGY DEVELOPMENT LLC;

    申请/专利号US201715495126

  • 发明设计人 YAN SOLIHIN;

    申请日2017-04-24

  • 分类号G06F9/50;G06F12/0806;G06F9/48;G06F12/0875;

  • 国家 US

  • 入库时间 2022-08-21 13:48:10

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