Single-stage arbiter/scheduler for a memory system comprising a volatile memory and a shared cache

摘要

Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DRAM) for a predetermined number of future clock cycles. The DRAM is electrically coupled to a system on chip (SoC). Based on the future memory state data, one of a plurality of pending memory transactions is selected that speculatively optimizes DRAM efficiency. The selected memory transaction is sent to a shared cache controller. If the selected memory transaction results in a cache miss, the selected memory transaction is sent to a DRAM controller.