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SINGLE-STAGE ARBITER/SCHEDULER FOR A MEMORY SYSTEM COMPRISING A VOLATILE MEMORY AND A SHARED CACHE
SINGLE-STAGE ARBITER/SCHEDULER FOR A MEMORY SYSTEM COMPRISING A VOLATILE MEMORY AND A SHARED CACHE
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机译:包含易失性内存和共享缓存的内存系统的单阶段调整器/调度程序
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摘要
Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DRAM) for a predetermined number of future clock cycles. The DRAM is electrically coupled to a system on chip (SoC). Based on the future memory state data, one of a plurality of pending memory transactions is selected that speculatively optimizes DRAM efficiency. The selected memory transaction is sent to a shared cache controller. If the selected memory transaction results in a cache miss, the selected memory transaction is sent to a DRAM controller.
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