Circuitry that performs floating-point operations on an integrated circuit is provided. The circuitry may execute a floating-point operation by decomposing the floating-point operation into multiple steps and decomposing the floating-point number on which to perform the floating-point operation into multiple portions. The circuitry may include storage circuits that store at least some results of the multiple steps, and memory access operations may be performed using some portions of the floating-point number. The circuitry may use arithmetic floating-point and arithmetic fixed-point circuits to implement Taylor series expansion circuits that may perform a subset of the multiple steps, thereby reducing the complexity of the subset of these steps.
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