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Dual-loop programmable and dividerless clock generator for ultra low power applications
Dual-loop programmable and dividerless clock generator for ultra low power applications
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机译:用于超低功耗应用的双环路可编程无分频时钟发生器
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摘要
A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region.
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