Device and method for implementing fast fourier transform/discrete fourier transform

摘要

A device for implementing FFT/DFT is disclosed, comprising: a first multiplier, a second multiplier, a first adder, a second adder, a first multiplexer, a second multiplexer, a first accumulator register, a second accumulator register and a negation controller, wherein the first adder is configured to accumulate the output signals of the first multiplexer, the first multiplier and the second multiplier and input an accumulated signal to the first accumulator register; the second adder is configured to accumulate the output signals of the second multiplexer, the first multiplier and the second multiplier and input an accumulated signal to the second accumulator register; the first accumulator register is configured to output the output signal of the first adder or feed the same back to the first multiplexer; and the second accumulator register is configured to output the output signal of the second adder or feed the same back to the second multiplexer.