METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A PROCESSOR BY POWERING DOWN AN INSTRUCTION FETCH UNIT

摘要

An apparatus and method are described for reducing power consumption in a processor by powering down an instruction fetch unit. For example one embodiment of a method comprises: detecting a branch the branch having addressing information associated therewith; comparing the addressing information with entries in an instruction prefetch buffer to determine whether an executable instruction loop exists within the prefetch buffer; wherein if an instruction loop is detected as a result of the comparison then powering down an instruction fetch unit and/or components thereof; and streaming instructions directly from the prefetch buffer until a clearing condition is detected.