DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING

摘要

Abstract of the Disclosure One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers (Figures 14 and 16). This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates (Figures 9A-B), each including a reversibly switchable interconnection between a number of address lines (910-912 and 920-922), or address-line-derived signal hues and an output signal line (914 and 924). Each reversibly switchable interconnection includes one or more reversibly switchable elements (906-90S and 916-918). In certain demultiplexer embodiments, NMOS (102) and/or PMOS transistors (206) are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors (410, 412 and 411, 413; 1502) are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines (1602, 1604) and additional switchable interconnections (1610) so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.