Method and system adaptive filtering based on a subband error

摘要

A method of adaptive filtering adjusted by at least one least square algorithm LMS based on a sub-band error, comprising: receiving, by an adaptive filter, an input signal, perform processing adaptive filtering on the signal input based on a weighting factor adaptive filtering currently stored in the adaptive filter in order to obtain L signal adaptive filtering, and transmit the signals L adaptive filtering to a subtractor; receiving, by the subtractor, a reference signal and the L signal adaptive filtering, perform a calculation based on the reference signal and the L signal adaptive filtering to obtain an error signal, and transmit the error signal to a filter subband error, wherein the reference signal is a signal generated after the input signal passes through a real channel; receiving, by the subband filter error, the error signal, performing an analysis filtering processing on subband error signal to obtain N subband error signals, and transmitting the N subband signals error updater adaptive weighting, receiving, by 20 an analysis filter input signal, the input signal, performing a filter processing analysis subband of the input signal to obtain N signals subband input, and transmitting the N signals input subband adaptive weighting the updater; and receiving, by the adaptive weighting updater, the N subband error signals and the M sub signals input band, calculation performed in function of the N subband error signals and the M subband signals input for a new weighting of adaptive filtering, and replace the weighting adaptive filtering currently stored in the adaptive filter by reweighting adaptive filtering; wherein the adaptive filter has L branches comprising a first branch to a Lth branch, and each branch has an input port and an output port, where L is a positive integer; when L is equal to 1, M multipliers M-1 adders and M-1 retarders clock M are arranged in the Lesima branch where the multiplier M is a multiplier 0 to a multiplier M-1, M-1 adders They are an adder 1 to an adder M-1 and M-1 clock retarders are a retarder M 1 M clock to a clock M- 1 M retarder; each retarder has an input port and an output port, each multiplier having an input port and an output port and each adder has two input ports and an output port, M is a positive integer, and a port input Lth branch is connected to input ports of the multiplier 0 to multiplier M-1, a port multiplier output 0 is connected to an input port retarder one clock M, an output port of each a multiplier 1 to the multiplier M-1 is connected to an input port of each of the adder 1 to adder M-1 and an output port of each retarder one clock M retarder M-1 clock M is connected to the other input port of adder adder 1 to M-1; then receiving, by an adaptive filter from an input signal, performing a processing adaptive filtering on the input signal according to a weighting adaptive filtering currently stored in the adaptive filter so that a signal is obtained adaptive filtering comprises: in the 1st branch, receiving, by each multiplier 0 to multiplier M-1, the input signal through the input port the Lth branch, and perform a multiplication on the input signal a weighting function stored adaptive filter in each of the multipliers, for a multiplier output signal generated by each multiplier multiplying 0 to M-1; providing, at the output, each multiplier 0 to multiplier M-1, through an output port of each multiplier 0 to multiplier M-1, the output signal of the multiplier generated by each multiplier 0 the multiplier M-1; effected for each retarder one clock M retarder M-1 clock M, processing clock delay M on a signal received at an input port of each retarder one clock M retarder M-1 M clock to obtain a clock delay signal M generated by each one clock retarder retarder M M M-1 clock; providing, at the output, each retarder one clock M retarder M-1 clock M, through the output port of each retarder one clock M retarder M-1 clock M, the signal M clock delay generated by each one clock retarder retarder M M M-1 clock; performing, by the adder 1 to adder M-1, processing of addition on the signals received via two ports 60 entry corresponding to each of the adder 1 to adder M-1, to obtain an output signal of the adder generated by each adder of the adder 1 to M-1, and provide, at the output, each adder of the adder 1 to M-1, through a corresponding output port to each of the adder 1 to adder M- 1, the output signal of the adder generated by each adder of the adder 1 to M-1; and when L is greater than 1, a retarder clock (L-1), M multipliers M-1 adders and M-1 retarders clock M are arranged in the Lth branch, where the multipliers M are a multiplier 0 to M- 1 multiplier, the M-1 adders are an adder 1 to an adder M-1 and M-1 clock retarders are a retarder M 1 M clock a retarder M-1 M clock; each retarder has one input port and output port, each multiplier having an input port and an output port and each adder has two input ports and an output port; and in the Lth branch, an input port of the Lth branch is connected to an input port retarder clock (L-5 1), an output port retarder clock (L-1) is connected to input ports of all multipliers, a port multiplier output 0 is connected to an input port retarder one clock M, an output port of each of the multiplier 1 to the multiplier M-1 is connected to a input port of each of the adder 1 to adder M-1, and an output port of each retarder one clock M retarder M-1 clock M is connected to another input port of each of the adder 1 M-1 to the adder; then receiving, by an adaptive filter from an input signal, performing processing adaptive filtering on the input signal according to a weighting adaptive filtering currently stored in the adaptive filter in order to obtain a signal adaptive filtering comprises: in the Lth branch, receiving, by the retarder clock (L-1) of the input signal through the input port retarder clock (L-1), and performing a processing clock delay (L-1) on the input signal to generate a signal clock delay (L-1); providing, at the output, the clock retarder (L-1), the clock delay signal (L-1) through the output port clock retarder (L-1); receiving, by each multiplier 0 to multiplier M-1, the signal clock delay (L-1) through the inlet port of Lesima branch, and perform a multiplication on the delay signal clock ( L-1) based on a weighting adaptive filtering stored in each of the multipliers, to obtain an output signal of the multiplier generated by each multiplier multiplying 0 to M-1; providing, at the output, each multiplier 0 to multiplier M-1 through an output port of each multiplier 0 to multiplier M-1, the output signal of the multiplier generated by each multiplier 0 to multiplier M-1; performing, by each retarder one clock M retarder M-1 clock M, processing clock delay M on a signal received at an input port of each retarder one clock M retarder M-1 M clock, in order to obtain a delay signal generated by each one clock retarder retarder M M M-1 clock; providing, at the output, each retarder one clock M retarder M-1 clock M through the output port of each retarder one clock M retarder M-1 clock M, the signal delay generated by each one clock retarder retarder M M M-1 clock; perform, for each of the adder 1 to adder M-1, processing of addition on the signals received via two input ports corresponding to each of the adder 1 to adder M-1, in order to obtain a signal output adder generated by each adder 1 to adder M-1, and provide, at the output, each of the adder 1 to adder M-1, through a corresponding output port to each of the adder 1 to M-1 adder, the adder output signal generated by each adder of the adder 1 to M-1.