首页> 外国专利> IMPROVED VERTICAL THYRISTOR MEMORY WITH MINORITY CARRIER LIFETIME REDUCTION

IMPROVED VERTICAL THYRISTOR MEMORY WITH MINORITY CARRIER LIFETIME REDUCTION

机译:减少了少数运营商寿命的改进的垂直晶闸管存储器

摘要

Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.
机译:本文描述了用于减少存储器阵列中的少数载流子的设备和方法。少数载流子在ON单元和OFF单元之间扩散,从而在写操作期间引起干扰,并降低了单元的保留寿命。描述了具有绝缘沟槽的垂直晶闸管存储阵列的少数载流子寿命杀手(MCLK)区域架构。这些MCLK区域鼓励少数载流子的重组。具体地,描述了由沿着晶闸管阵列的阴极线嵌入的导体形成的MCLK区域以及掺杂剂MCLK区域,以及用于制造具有MCLK区域的晶闸管存储单元的方法。

著录项

  • 公开/公告号WO2017139286A1

    专利类型

  • 公开/公告日2017-08-17

    原文格式PDF

  • 申请/专利权人 KILOPASS TECHNOLOGY INC.;

    申请/专利号WO2017US16865

  • 发明设计人 CHENG CHARLIE;AXELRAD VALERY;LUAN HARRY;

    申请日2017-02-07

  • 分类号H01L27/08;H01L27/102;

  • 国家 WO

  • 入库时间 2022-08-21 13:30:06

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