- TECHNIQUES TO ACHIEVE AREA REDUCTION THROUGH CO-OPTIMIZING LOGIC CORE BLOCKS AND MEMORY REDUNDANCIES

摘要

Techniques for achieving size reduction of embedded memory arrays through determining a spare core layout are disclosed. In an embodiment, input parameters including global process parameters are combined with design properties to calculate yield values corresponding to potential redundancy configurations for the die. The resulting yields are compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured to have one or more spare cores (without any redundant memory therein) is equivalent to or yields a yield of die with conventional memory redundancies. In some exemplary cases, memory redundancy is removed from the cores. Another embodiment provides a semiconductor structure comprising an array of redundant cores, wherein each core comprises a composition of logic structures and memory arrays, and at least one of the memory arrays of each redundant core is selected from the group consisting of low redundancy and column redundancy It is implemented without at least one.