3 THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NONVOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A DOUBLE-GLOBAL-BIT-LINE ARCHITECTURE

摘要

The present invention provides a three-dimensional array that is specially adapted to memory elements that invert the level of electrical conductivity in response to a voltage difference applied to the memory elements. Memory elements are formed intersecting a plurality of planes located at different distances on a semiconductor substrate. A two-dimensional array of bit lines to which memory elements of all planes are connected is oriented vertically through the plurality of planes from the substrate. A dual global bit line architecture provides a pair of global bit lines for each bit line to connect to a row of memory elements in parallel. While the second pair of each pair allows the local bit lines in the adjacent column to set the correct voltage to remove the leakage current between adjacent rows of local bit lines, the first pair of each pair is sensed .