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REFRESH SCHEME FOR MEMORY CELLS WITH NEXT BIT TABLE

机译:带有下一位表的记忆细胞刷新方案

摘要

The memory refresh control scheme allows flexible internal refresh rates based on the external 1X refresh rate and allows skipping the refresh cycle for the strong memory rows based on the external 1X refresh rate. The memory controller performs a memory refresh by reading the refresh address from the refresh address counter, reading the weak address from the weak address table, and generating the next weakest address value based at least in part on the next bit sequence associated with the weak address do. The memory controller compares the refresh address with the weak address and the next weakest address value. Based on the comparison, the memory controller selects between skipping the refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.
机译:存储器刷新控制方案允许基于外部1X刷新率的灵活内部刷新率,并允许基于外部1X刷新率跳过强存储行的刷新周期。存储器控制器通过以下方式执行存储器刷新:从刷新地址计数器读取刷新地址,从弱地址表中读取弱地址,并至少部分地基于与弱地址相关联的下一个位序列生成下一个最弱地址值做。存储器控制器将刷新地址与弱地址和下一个最弱地址值进行比较。基于比较,存储器控制器在跳过刷新周期,刷新刷新地址,刷新弱地址以及刷新刷新地址和弱地址两者之间进行选择。

著录项

  • 公开/公告号KR101766875B1

    专利类型

  • 公开/公告日2017-08-09

    原文格式PDF

  • 申请/专利权人 퀄컴 인코포레이티드;

    申请/专利号KR20167017484

  • 发明设计人 동 시앙유;김 정필;서 중원;

    申请日2014-11-20

  • 分类号G11C11/406;G06F12/02;

  • 国家 KR

  • 入库时间 2022-08-21 13:25:00

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