sram cell comprising a memory and a p - n - tfet trust fund for east timor

摘要

An SRAM memory cell (100) comprising: - an n-TFET (102) and a p-TFET (104), - a storage node (106) formed by connecting a first electrode of the n-TFET to a first electrode the p-TFET (drains or sources), - a control circuit (200) capable of applying supply voltages to second electrodes of the n-TFETs and p-TFETs (sources or drains), in which the control circuit is configured to provide: - in a retention mode, polarizing supply and polarization voltages by reversing the n-TFETs and p-TFETs to obtain band-to-band tunneling conduction current in the n-TFETs and p-TFETs. -TFET; in a one-bit write, supply and polarization voltages direct bias the n-TFET and p-TFET such that one is blocked and the other is passing.