Processors, methods, and systems to relax synchronization of accesses to shared memory

摘要

A processor comprises a plurality of logical processors, with a first of these processors executing software including conditional memory instructions; with a decode unit to convert the conditional memory access instruction(s) to unconditional memory access operations when the processor is in a relaxed memory access synchronisation mode. The unconditional memory access instructions preferably access a first portion of a memory without respecting memory access synchronisation. The conditional memory access instructions preferably comprise conditional load or conditional store instructions which are converted into respective unconditional instructions; or a load-link and store-conditional pair of instructions which are converted into a single unconditional store operation; or a read-modify-write instruction that is converted into a single unconditional write operation. The processor preferably has one or more architecturally visible bits to indicate being in the relaxed mode, with these bits preferably modifiable by software. Preferably, the processor is in the relaxed mode when only a single thread is running, and/or or when only one thread will access an associated shared memory, and/or no other thread will be observing the associated shared memory.