Apparatus and a method for processor core self-testing are disclosed. The apparatus 10 comprises processor core circuitry 20 to perform data processing operations by executing data processing instructions. Separate self-test control circuitry 14 causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry. The apparatus may be such that the export of the self-test data maybe be exported after returning to the first state. The self-test support circuitry may, for example, comprise a dedicated self-test path from the processor to the self-test control circuitry, instruction type indication circuitry, memory transaction request indication circuitry, or memory transaction blocking circuitry.
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