Fast and accurate frame synchronization in FSK based receivers

摘要

A frame sync detecting circuit and FSK receiver wherein, as shown in the drawing, a moving average value (–¡) is sequentially derived from oversample values (solid line) of a received word pattern, for given symbol periods, and a difference between the moving average value and an average value for the given symbol periods in a given sync word pattern is determined as DC offsets ”f. Subsequently, the DC offset ”f is subtracted from the received word pattern, and a correlation processing with respect to the sync word pattern is performed to determine a correlation value designated by the black circle (€¢). Then, if the correlation value exceeds a predetermined threshold value, it is determined that a sync word candidate has been received, and symbol values P11' to P20' of the received word pattern after the DC offset correction are compared with respective symbol values of the sync word pattern. If errors in all the symbols are within a given range, a sync word pattern detection is ultimately determined.