Clock recovery method and clock recovery arrangement for coherent polarisation multiplex receivers

摘要

Component signal values (XI, XQ; YI, YQ) are derived from component signals (xi, xq, yi, yq) and fed to least one fixed equaliser (EQU) which generates equalizer output signals (X IE , X QE , Y IE , Y QE ) . These signals are fed to phase error detectors (PD3, PD4) generating phase error signals (X PE3 Y PE4 ). These phase error signals (X PEi ) are combined with further phase error signals (X PE1 , Y PE2 ) derived by further error detectors (PD1, PD2) receiving signal values from further equalizers and/or the component signal values (XI, XO ; YI, YQ) directly from sample units (15, 16).