首页> 外国专利> VIA SELF ALIGNMENT AND SHORTING IMPROVEMENT WITH AIRGAP INTEGRATION CAPACITANCE BENEFIT

VIA SELF ALIGNMENT AND SHORTING IMPROVEMENT WITH AIRGAP INTEGRATION CAPACITANCE BENEFIT

机译:通过气隙集成电容优势进行自我校准和改进

摘要

A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization; and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.
机译:一种方法,包括在集成电路结构的金属线之间形成牺牲材料。在牺牲材料上形成掩模;在形成掩模之后,去除牺牲材料以在金属线之间留下空隙。一种设备,包括集成电路基板;衬底上的第一金属化层;第二次金属化;以及设置在第一金属化层和第二金属化层之间的掩模,该掩模包括介电材料,其具有选择的孔隙率以允许通过其的质量传输,其中第一金属化层和第二金属化层的每一个包括多条金属线,并且第一金属化层和第二金属化层中的至少一个的相邻金属线的一部分被空隙分开。

著录项

  • 公开/公告号EP3238237A4

    专利类型

  • 公开/公告日2018-08-08

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号EP20140909202

  • 发明设计人 SINGH KANWAL JIT;MYERS ALAN M.;

    申请日2014-12-22

  • 分类号H01L21/768;H01L21/84;

  • 国家 EP

  • 入库时间 2022-08-21 13:18:42

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