METHOD FOR PROTECTING AN FPGA AGAINST AN UNAUTHORIZED USE OF THE RTL SOURCE CODE

摘要

A method of protecting an FPGA from unauthorized use of the RTL source code,wherein the FPGA consists of many logic elements (LE), which can be connected to one another via a grid,wherein a logic element (LE) contains in each case a logic circuit (L; L1, L2, L3) and a register (R1),the configuration data being generated by a synthesis tool from the RTL source code, which are loaded into the logic circuits (L; L1, L2, L3) and the registers (R1, R2) when the supply voltage of the FPGA is switched on,wherein the synthesis tool in the generation of the configuration data in addition to the RTL source code, an instruction, in the form of a synthesis condition is supplied, with which at least one signal path (S) for a logic element (LE) is set so that in the operation of the FPGA on this signal path results in a runtime that is longer than one clock of the FPGA.