A method of protecting an FPGA from unauthorized use of the RTL source code

摘要

Method for protecting an FPGA from an unauthorized use of the RTL source code, wherein the FPGA consists of many logic elements (LE), which can be connected to one another via a grid, wherein a logic element (LE) in each case a logic circuit (L; L1, L2, L3 ) and a register (R1), wherein by a synthesis tool from the RTL source code, the configuration data are generated, which when turning on the supply voltage of the FPGA in the logic circuits (L; L1, L2, L3) and the registers (R1, R2) are loaded with the synthesis tool in the generation of the configuration data in addition to the RTL source code, a command, in the form of a synthesis condition, with which at least one signal path (S) for a logic element (LE) is set so that in Operation of the FPGA on this signal path results in a runtime that is longer than one clock of the FPGA.