BUFFER CAPACITY ADJUSTMENT CIRCUIT AND BUFFER CAPACITY ADJUSTMENT METHOD

摘要

PROBLEM TO BE SOLVED: To provide a buffer capacity adjustment circuit capable of improving the followability to capacity fluctuation of an FIFO without increasing the circuit scale.;SOLUTION: A buffer capacity adjustment circuit 100 includes: an FIFO 101; a PLL circuit 102 that generates a read-out clock for reading out at different rate relative to writing of data on the FIFO 101 and supplies the same to the FIFO 101; and a monitor circuit 103 that monitors the present buffer amount of the FIFO 101 and outputs an adjustment signal for adjusting the speed of the read-out clock depending on a difference of the present buffer amount with respect to a center value of the buffer capacity of the FIFO 101 to the PLL circuit 102 to converge the present buffer amount to the center value.;SELECTED DRAWING: Figure 1;COPYRIGHT: (C)2018,JPO&INPIT