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Data filter cache designs for enhancing energy efficiency and performance in computing systems

机译:数据过滤器高速缓存设计,用于提高计算系统的能效和性能

摘要

Certain embodiments herein relate to, among other things, designing data cache systems to enhance energy efficiency and performance of computing systems. A data filter cache herein may be designed to store a portion of data stored in a level one (L1) data cache. The data filter cache may reside between the L1 data cache and a register file in the primary compute unit. The data filter cache may therefore be accessed before the L1 data cache when a request for data is received and processed. Upon a data filter cache hit, access to the L1 data cache may be avoided. The smaller data filter cache may therefore be accessed earlier in the pipeline than the larger L1 data cache to promote improved energy utilization and performance. The data filter cache may also be accessed speculatively based on various conditions to increase the chances of having a data filter cache hit.
机译:本文的某些实施例尤其涉及设计数据高速缓存系统以增强能量效率和计算系统的性能。本文中的数据过滤器高速缓存可以被设计为存储存储在一级(L1)数据高速缓存中的数据的一部分。数据过滤器高速缓存可以驻留在L1数据高速缓存和主计算单元中的寄存器文件之间。因此,当接收和处理数据请求时,可以在L1数据缓存之前访问数据过滤器缓存。在数据过滤器高速缓存命中时,可以避免对L1数据高速缓存的访问。因此,与较大的L1数据高速缓存相比,可以在管道中更早地访问较小的数据筛选器高速缓存,以提高能源利用率和性能。还可以基于各种条件来推测性地访问数据过滤器高速缓存,以增加命中数据过滤器高速缓存的机会。

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