POWER-GOOD DETECTOR FOR ULTRA-WIDE BAND TRANSMITTER WITH EMPHASIS ON LOW POWER CONSUMPTION

摘要

Systems, devices and methods are disclosed using a transmitter architecture to keep the transmitter in a deep sleep mode before activation/enabling. The transmitter tag comprises a power-good-detector, a first regulator and a second regulator. The power-good-detector includes a power-good-latch, a ring oscillator and a ripple counter. Upon disconnecting a GPIO pin from the ground, the power-good-latch sends a Bias_EN signal to the regulator. Upon receipt of the Bias_EN signal, the first regulator transmits a wakeup signal to the ring oscillator, which then starts sending the clock signals to the ripple counter. When the counted clock signals reach a threshold value, the ripple counter sends the power-good-digital signal to the flip flops. When the tag is in the reset mode, the power-good-digital signal is also low. When the power-good-digital signal goes from low to high, the tag is out of the reset mode.