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Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die

机译:用于在管芯之间的短信号路径的积层互连结构中形成腔的半导体器件和方法

摘要

In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path.
机译:在半导体器件中,第一半导体管芯被安装成其有源表面朝向临时载体。密封剂沉积在第一半导体管芯和临时载体上方。去除临时载体以暴露密封剂的第一侧和第一半导体管芯的有源表面。在第一半导体管芯的有源表面上方形成掩模层。在密封剂的第一侧上方形成第一互连结构。掩模层阻止在第一半导体管芯的有源表面上方的第一互连结构的形成。去除掩模层以在第一半导体管芯的有源表面上方形成腔。第二半导体管芯安装在空腔中。第二半导体管芯通过短信号路径电连接至第一半导体管芯的有源表面。

著录项

  • 公开/公告号US10068843B2

    专利类型

  • 公开/公告日2018-09-04

    原文格式PDF

  • 申请/专利权人 STATS CHIPPAC LTD.;

    申请/专利号US201213726467

  • 发明设计人 REZA A. PAGAILA;

    申请日2012-12-24

  • 分类号H01L23/522;H01L21/56;H01L23/31;H01L23/498;H01L23/538;H01L23/552;H01L25/065;H01L25;H01L21/768;H01L23/34;H01L23;H01L25/10;H01L25/16;

  • 国家 US

  • 入库时间 2022-08-21 13:01:42

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