METHOD FOR IMPROVING RUNTIME PERFORMANCE OF MULTI-CLOCK DESIGNS ON FGPA AND EMULATION SYSTEMS USING ITERATIVE PIPELINING

摘要

The present invention relates to a method to improve the runtime performance of designs with multiple clocks on FPGA's and emulation system. In the method, the compile frequency (F_Max) for complex design is improved by breaking-up the critical timing path of the design by inserting pipeline flops iteratively which are clocked at faster available clock frequencies. The method is easily implemented in a design where the clocks are of different frequencies but derived from the same primary clock i.e. the clocks are synchronous to each other and ratio of highest to lowest clock frequencies is more than or equal to 2. It enables optimal usage of emulator up time and hardware area.