METHODS AND SYSTEMS FOR TIMING CONSTRAINT GENERATION IN IP/SoC DESIGN

摘要

This disclosure relates generally to methods and systems for reducing complexity of synthesis and static timing analysis (STA) part in SoC design arising out of designs received from multiple sources of IC blocks. In one embodiment, an integrated circuit design apparatus is provided. The apparatus comprises one or more hardware processors and one or more memory units storing instructions executable by the one or more hardware processors for obtaining register transfer level code for an integrated circuit design block; parsing the register transfer level code to extract a pragma included in the register transfer level code for the integrated design block; determining a timing constraint from the extracted pragma; synthesizing a netlist for an integrated circuit design including at least one instance of the integrated circuit design block, using the determined timing constraint; and providing the netlist for use in an integrated circuit manufacturing process.