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LOCALITY-AWARE AND SHARING-AWARE CACHE COHERENCE FOR COLLECTIONS OF PROCESSORS
LOCALITY-AWARE AND SHARING-AWARE CACHE COHERENCE FOR COLLECTIONS OF PROCESSORS
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机译:本地感知和共享感知缓存了处理器集合的一致性
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摘要
A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.
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