High-throughput low-latency erasure error correction in an integrated circuit

摘要

An example method of erasure error correction in an IC includes receiving input data from a channel coupled to the IC, determining a bit pattern indicating survived blocks and erased blocks of a plurality of blocks in the input data and determining a number of integers, in a finite set of integers, greater than or less than an integer representing the bit pattern, the finite set of integers representing a finite set of possible values of the bit pattern based on an (m, k) erasure coding scheme. The method further includes generating an address for a memory, which stores a plurality of pre-computed decoding matrices based on the (m, k) erasure coding scheme, from the determined number of integers to obtain a pre-computed decoding matrix associated with the bit pattern. The method further includes recovering the erased blocks through matrix multiplication using the pre-computed decoding matrix and the survived blocks as parametric input.