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Multi-threaded processor interrupting and saving execution states of complex instructions of a first thread to allow execution of an oldest ready instruction of a second thread
Multi-threaded processor interrupting and saving execution states of complex instructions of a first thread to allow execution of an oldest ready instruction of a second thread
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机译:多线程处理器中断并保存第一线程的复杂指令的执行状态,以允许执行第二线程的最旧的就绪指令
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摘要
A first entry, when outputting an instruction stored in the first entry to a first arithmetic unit and when an execution cycle number of the instruction stored in the first entry is equal to or more than a threshold value, outputs a use inability signal of the first arithmetic unit to a second entry, a reservation station includes a controller configured to, when the use inability signal of the first arithmetic unit is output and then a use inability discontinuation condition is satisfied, perform control to discontinue execution of the first arithmetic unit, store a state of the first arithmetic unit in a storage element, and discontinue output of the use inability signal of the first arithmetic unit, and the second entry, when output of the use inability signal of the first arithmetic unit is discontinued, outputs an instruction stored in the second entry to the first arithmetic unit.
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